1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing the same, and particularly relates to a semiconductor device comprising a vertical MOS transistor having a three-dimensional structure and a method for manufacturing the same.
2. Description of Related Art
Planar MOS transistors are generally used as MOS transistors formed on a semiconductor substrate. However, a problem with planar MOS transistors is that increased miniaturization to enhance integration results in pronounced short channel effects and increased sub-threshold current.
Methods for increasing the concentration of substrate impurities are effective as methods for controlling sub-threshold current, but increasing the concentration of impurities increases the junction leak current. An increased junction leak current is not much of a problem in transistors for logic circuits, but leads to a loss of refresh properties in cell transistors for DRAM (Dynamic Random Access Memory). It is therefore difficult to increase the concentration of impurities in cell transistors for DRAM.
Progress has been made in the research on MOS transistors having a three-dimensional structure, such as RCAT (Recess-Channel-Array Transistor) and Fin FET, as well as in applications thereof in products, as DRAM cell transistors in order to solve the problems noted above. However, as with planar MOS transistors, the source regions and drain regions of MOS transistors such as RCAT and FinFET are formed in different planes on the semiconductor substrate, giving a structure in which the on current flows along the surface of the semiconductor substrate, and it is therefore difficult to sufficiently increase integration.
By contrast, vertical MOS transistors in which the on current flows vertically have recently been proposed (see published Japanese Translation of PCT Application No. 2002-541667 and Japanese Patent Application Laid-open Nos. H5-121693 and H7-273221). Higher integration can be achieved in vertical MOS transistors because the source and drain regions are formed in substantially the same plane on the semiconductor substrate.